1. Field of the Invention
The present invention relates to an output buffer with an offset cancellation structure and an offset cancellation method for a liquid crystal display (LCD) source driver, and more particularly, to an output buffer with an offset cancellation structure and an offset cancellation method for an LCD source driver having a benefit of less transistor count.
2. Description of the Prior Art
A liquid crystal display (LCD) source driver is utilized for outputting voltages to an LCD panel according to pixel data required to be displayed. In order to drive pixel units on the LCD panel, an output buffer is always implemented in an output terminal of each channel of the source driver. The output buffer should be able to drive the pixel units with a wide range of gray scale or brightness, and thereby includes an operational amplifier having high loop gain and high slew rate. More importantly, the operational amplifier should have a rail-to-rail input and rail-to-rail output structure, to be adapted to a wide range of pixel data, which may extend from the ground voltage to the power supply voltage of the output buffer.
However, most operational amplifiers have offset between input terminals; that is, there may be a slight voltage difference between the operational amplifier's positive input terminal and negative input terminal; this offset causes an error in the pixel data outputted by the output buffer.
Several offset cancellation techniques have been disclosed. One of the common offset cancellation techniques is chopper circuit. Please refer to FIG. 1A and FIG. 1B, which are schematic diagrams of an output buffer 10 using the chopper offset cancellation technique. As shown in FIGS. 1A and 1B, the output buffer 10 includes a closed loop operational amplifier 100, where the pixel data signal V_DATA is inputted to an input terminal of the operational amplifier 100, and another input terminal is connected to the output terminal of the operational amplifier 100, to form the closed loop structure. There is an offset voltage V_OS between input terminals of the operational amplifier 100, as illustrated to be a voltage source coupled to the positive input terminal of the operational amplifier 100. The chopper circuit applies two phases to average out the offset voltage V_OS. A switch module 102 is applied to switch the output buffer 10 between the two phases, one of which is illustrated in FIG. 1A and the other is illustrated in FIG. 1B.
In FIG. 1A, the pixel data signal V_DATA is inputted to the positive input terminal of the operational amplifier 100, and the negative input terminal of the operational amplifier 100 is coupled to the output terminal. In this case with consideration of the offset voltage V_OS, the output signal of the operational amplifier 100 will be equal to V_DATA plus V_OS. In FIG. 1B, the pixel data signal V_DATA is inputted to the negative input terminal of the operational amplifier 100, and the positive input terminal of the operational amplifier 100 is coupled to the output terminal. In this case with consideration of the offset voltage V_OS, the output signal of the operational amplifier 100 will be equal to V_DATA minus V_OS. If the switch module 102 keeps switching between the two phases, the output signal of the operational amplifier 100 may be continuously switched between V_DATA+V_OS and V_DATA−V_OS. In such a condition, the long-term average of the output signal will be V_DATA, and the offset voltage V_OS is cancelled.
Furthermore, FIG. 2 illustrates the structure of the operational amplifier 100. In order to be adapted to a wide range of pixel data, the operational amplifier 100 should have rail-to-rail input and rail-to-rail output structure. For the realization of rail-to-rail input, the operational amplifier 100 includes two input stages, one of which has a differential pair of NMOS transistors and the other has a differential pair of PMOS transistors. In both differential pairs, the gate terminals of transistors receive input signals V_IP and V_IN from the positive and negative input terminals, respectively. The operational amplifier 100 is controlled by bias voltages V_BP1, V_BP2, V_BP3, V_BN1, V_BN2 and V_BN3, and outputs an output signal V_OUT. In addition, since the output buffer 10 is switched between two phases, the operational amplifier 100 should be switched accordingly and there are 12 switches deployed in the operational amplifier 100. In such a condition, the operational amplifier 100 requires 20 transistors for rail-to-rail structure and high driving capability, as well as 24 transistors for the 12 switches. There are 44 transistors in the operational amplifier 100. In consideration of 44 transistors in the operational amplifier 100 and 8 transistors for the 4 chopper switches in the switch module 102 (as shown in FIGS. 1A and 1B), the output buffer 10 using the chopper offset cancellation technique totally requires 52 transistors, which occupies a significant area in the source driver.
In order to reduce the transistor count, other offset cancellation techniques are proposed, e.g., the auto-zero technique. However, the performance of transistor reduction may still be unsatisfactory. Thus, there is a need for providing a more preferable offset cancellation circuit to further reduce the transistor count in the output buffer of the LCD source driver.